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[VHDL-FPGA-Verilog] fifo的vhdl原代码

Description: 本文为verilog的源代码-In this paper, the source code for Verilog
Platform: | Size: 22528 | Author: 艾霞 | Hits:

[Books] 可编程逻辑系统的VHDL设计技术_0

Description: 可编程逻辑系统的VHDL设计技术,该本书首先对VHDL语言进行了阐述,然后用alter公司的产品进行举例!-programmable logic system VHDL design technology, the first book of VHDL expounded, and then alter the company's products, for example!
Platform: | Size: 11019264 | Author: 高操 | Hits:

[SCM] P.H.Y_programer

Description: 单片机的程序集.大家可以参考一下.我想做一个更好的程序集及电路板.大约在10月份完成.请有兴趣的关注一下.当然我还要做一个通信的vhdl的仿真.-SCM suite. We can take a look. I would like to do a better procedures for collecting and circuit boards. About October completion. those interested in the look. of course, I still have to do a communications VHDL simulation.
Platform: | Size: 28672 | Author: 潘 应 云 | Hits:

[SCM] PinYin_InputMethod_C51

Description: 用C51实现的拼音输入法,这是改写的网友 embuffalo、独步上载在www.21ic.com自由发布区的由张凯原作的51上的拼音输入法程序。 原作使用了一个二维数组用以查表，我认为这样比较的浪费空间，而且每个字表的索引地址要手工输入，效率不高。所以我用结构体将其改写了一下。就是大家现在看到的这个。 因为代码比较的大，共有6,000多汉字，这样就得要12,000 byte来存放GB内码，所以也是没办法的 :-( 编译结果约为3000h,因为大部分是索引表，代码优化几乎无效。 在Keil C里仿真芯片选用的是华邦的W77E58，它有32k ROM, 256B on-chip RAM, 1K on-chip SRAM (用DPTR1指针寻址,相当于有1K的片上xdata)。条件有限，没有上片试验，仿真而已。 打算将其移植到AVR上，但CodeAVRC与IAR EC++在结构体、指针的定义使用上似乎与C51不太一样，现在还未搞定。还希望在这方面有经验的网友能给予指导。-C51 with the Pinyin input method, which is rewritten netizens embuffalo. Unrivaled www.21ic.com available in the free publication of the original work by Kai-51 on the Pinyin input method procedures . Appreciate the use of a two-dimensional array for the look-up table, I think this is a waste of space. Each of the characters but the index table to manually input address, efficiency is not high. I use the structure to rewrite a bit. We see now is this. Because the code comparison, a total of 6, more than 000 Chinese characters, this must be 12, byte to store 000 GB code, is not the way to compile results :-( about 3000h. because most of the index table. Code Optimization almost ineffective. Keil in the C simulation uses the chip in W77E58 Winbond, It has 32 k ROM 256B on-chip RAM, 1K on-chi
Platform: | Size: 14336 | Author: Jawen | Hits:

[Multimedia Develop] VBuffer_1c6

Description: 视频采集并锁存到SDRAM中的完整代码，运行环境为QII，VHDL与标准参数宏模块调用混合设计　是学习视频采集的很好的参考-Video Capture SDRAM and latches to the integrity code, the operating environment for QII. VHDL standard parameter-called hybrid module is designed to study the Video Capture good reference
Platform: | Size: 4133888 | Author: 刘留 | Hits:

[VHDL-FPGA-Verilog] BRAM2DRAM

Description: FPGA内嵌的BRAM资源很少，此代码为DRAM代码风格，可以极大程度上减少FPGA内嵌资源的消耗。txt文档中含源代码，直接粘成vhdl即可-FPGA embedded BRAM few resources, the code for the DRAM code style, you can significantly reduce resource consumption embedded FPGA. txt document containing the source code directly into VHDL can be sticky
Platform: | Size: 2048 | Author: 苗苗 | Hits:

[File Format] ram_da

Description: 将AD转换得到的八位数据存入RAM，存1000个点，然后通过串行DA读出，DA芯片为TLV5638,AD芯片为tlc0820ac，RAM为FM25L16-AD conversion will be the eight data into RAM, keep 1000 points, and then read out through the DA serial, DA chips for the TLV5638, AD chips for tlc0820ac, RAM for FM25L16
Platform: | Size: 650240 | Author: 王力 | Hits:

[VHDL-FPGA-Verilog] 32×4bitRAM

Description: 32×4bit 的RAM设计。VHD语言。能在ISE上仿真。-32 × 4bit the RAM design. VHD language. The simulation in ISE.
Platform: | Size: 3072 | Author: 张军 | Hits:

[Embeded-SCM Develop] testram_1

Description: EDA实验--RAM实验:利用-MegaWizard Plug-In Manager创建一个16×8的RAM，通过编程对RAM进行读写并在显示器上显示。 本例使用三个按键PSW3，PSW2，PSW1，分别对应顶层文件中的x，y，we，we＝1对RAM写，xy＝11时，写入10101011；当xy＝01时，写入01010101；当xy＝10时，写入10101010。we＝0时，对RAM读出。三个按键按下时为0，当PSW1健按下时对RAM进行读出。 -EDA Experimental RAM experiment: the use-MegaWizard Plug-In Manager to create a 16 × 8 of the RAM, through the programming of the RAM read and write and displayed on the monitor. This example uses three buttons PSW3, PSW2, PSW1, corresponding to top-level document x, y, we, we = 1 on RAM write, xy = 11, the write 10101011 when xy = 01 hours, write 01010101 when xy = 10, the write 10101010. we = 0 when read out of RAM. Press the three keys for 0, when PSW1 Kin-pressed to read out of RAM.
Platform: | Size: 4096 | Author: 黄龙 | Hits:

[VHDL-FPGA-Verilog] RAM

Description: 用VerilogHDL写的ram程序，对初学者会有帮助。-Writing the ram with VerilogHDL procedures will be helpful for beginners.
Platform: | Size: 271360 | Author: Blakeu | Hits:

[VHDL-FPGA-Verilog] ram

Description: a 16 by 4 ram is used for many applications as a basic component such as fifo and stack etc
Platform: | Size: 1024 | Author: sri | Hits:

[VHDL-FPGA-Verilog] all_ram_20081116.tar

Description: vhdl cod for ram.For sp3e
Platform: | Size: 1126400 | Author: Fl0rin | Hits:

[VHDL-FPGA-Verilog] ram32b

Description: VHDL code for 32 byte RAM
Platform: | Size: 1024 | Author: Davood | Hits:

[VHDL-FPGA-Verilog] RAM

Description: 用VHDL编写一个字长16位，容量128B的RAM控制实现程序，并进行设计综合和功能模拟 。含源程序，及实验要求。适合初学者学习使用。-VHDL prepared with a 16-bit word length, 128B of the RAM capacity to achieve process control and design of analog integrated and functional. Containing source code, and experimental requirements. Suitable for beginners learning to use.
Platform: | Size: 9216 | Author: 赵剑平 | Hits:

[Windows Develop] RAM

Description: Code for designing 16 bit RAM
Platform: | Size: 9216 | Author: Magic | Hits:

[Software Engineering] spartan6_fpga_blockram_user_guide

Description: Spartan6　FPGA中的块存储器使用指南，可以构建为FIFO，ROM，RAM，移位寄存器等。-Spartan6 FPGA block memory in the User Guide, you can build for FIFO, ROM, RAM, shift registers and so on.
Platform: | Size: 376832 | Author: james | Hits:

[VHDL-FPGA-Verilog] RAM.ZIP

Description: VHDL CODE FOR RAM AND ROM
Platform: | Size: 1024 | Author: praba | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 双口RAM模块源代码（VHDL）,用于开发FPGA的双口RAM，可以直接下载到工程中使用。-Dual-port RAM module source code (VHDL), for the development of FPGA' s dual-port RAM, can be directly downloaded to the project use.
Platform: | Size: 1024 | Author: wu | Hits:

[VHDL-FPGA-Verilog] doc

Description: BIST for RAMs using ASTRA: Transparent Built-In Self Test (BIST) schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric transparent BIST skips the signature prediction phase required in traditional transparent BIST schemes, achieving considerable reduction in test time. In symmetric transparent BIST schemes proposed to date, output data compaction is performed using either single-input or multiple-input shift registers whose characteristic polynomials are modified during testing. In this project, the utilization of accumulator modules for output data compaction in symmetric transparent BIST for RAMs is proposed. In this project, it has been demonstrated that accumulator based compaction scheme
Platform: | Size: 243712 | Author: sreekanth p | Hits:

[Education soft system] ReadWrite-RAM-VHDL-source-code

Description: This page of VHDL source code covers read RAM and write to RAM vhdl code. RAM stands for Random Access memory.It is a form of data storage for various applications. 1K refers 10 lines used for Address bus (as 2^10=1024) 8 refers Data Bus lines are 8 Hence, each location can store 8 bits (i.e. 1 byte each) ADR: in std_logc_vector (9 downto 0) D: inout std_logic_vector (7 downto 0) CS: in std_logic OE: in std_logic WR: in std_logic-This page of VHDL source code covers read RAM and write to RAM vhdl code. RAM stands for Random Access memory.It is a form of data storage for various applications. 1K refers 10 lines used for Address bus (as 2^10=1024) 8 refers Data Bus lines are 8 Hence, each location can store 8 bits (i.e. 1 byte each) ADR: in std_logc_vector (9 downto 0) D: inout std_logic_vector (7 downto 0) CS: in std_logic OE: in std_logic WR: in std_logic
Platform: | Size: 1024 | Author: ss | Hits:
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